1. Field of the Invention
This invention relates to a bias voltage generating circuit and an operational amplifier circuit, and more particularly to a bias voltage generating circuit and an operational amplifier circuit by which a plurality of bias voltages can be set at the same time with a resistor which is provided outside a semiconductor integrated circuit (IC).
2. Description of the Prior Art
An operational amplifier circuit which employs a MOS FET (insulating gate type field effect transistor) is conventionally known and disclosed, for example, in Japanese Patent Laid-Open Application No. 62-68308.
Referring to FIG. 3, there is shown an exemplary one of conventional operational amplifier circuits. The operational amplifier circuit shown includes a pair of N-channel MOS FETs Q.sub.A and Q.sub.B for differential amplification, and a pair of P-channel MOS FETs Q.sub.C and Q.sub.D which are connected to the drains of the differential amplification MOS FETs Q.sub.A and are Q.sub.B and constructed as a current mirror circuit. The operational amplifier circuit further includes an N-channel MOS FET Q.sub.E for level shifting. The MOS FET Q.sub.E is provided to drive a P-channel MOS FET Q.sub.F and an N-channel MOS FET Q.sub.G which are push-pull connected to each other by an output of the drain of the MOS FET Q.sub.B and an output of the source of the N-channel MOS FET Q.sub.E. The operational amplifier further includes an N-channel MOS FET Q.sub.H for generation of a bias voltage. The MOS FET Q.sub.H is connected between power source terminals +V and -V by way of a P-channel MOS FET Q.sub.I and an N-channel MOS FET Q.sub.J which are connected in series as a resistor. A pair of N-channel MOS FET transistors Q.sub.K and Q.sub.L form a constant-current source and are commonly biased by the bias voltage generator N-channel MOS FET Q.sub.H.
Since the resistance value of the P-channel MOS FET Q.sub.I and N-channel MOS FET Q.sub.J which are connected in series as a resistor disperses about .+-.20 to .+-.30% when they are constituted as an IC, their operating current must necessarily be set high, and as a result, there is high power consumption which is undesirable.
Meanwhile, in case such operational amplifier circuit is provided with a plurality of channels and the N-channel MOS FET transistors Q.sub.K and Q.sub.L are individually biased by the operational amplifiers, since the voltage lines are drawn between the bias voltage generation N-channel MOS FETs Q.sub.H and the constant-current source transistors Q.sub.K and Q.sub.L noise is readily picked up. Besides, since the N-channel MOS FETs Q.sub.J and Q.sub.H and the P-channel MOS FETs Q.sub.I for generation of a bias voltage are separately provided. A large chip size is required for the IC which is undesirable.